MP3 Decoder Master's Thesis

This is Krister Lagerstrom's Master's Thesis for the degree in Computer Science and Engineering (Swedish: "Civilingenjör i Datateknik") . It was done at Chalmers University of Technology in Gothenburg, Sweden.

Abstract

Digital compression of audio data is important due to the bandwidth and storage limitations inherent in networks and computers. Algorithms based on perceptual coding are effective and have become feasible with faster computers. The ISO standard 11172-3 MPEG-1 layer III (a.k.a. MP3) is a perceptual codec that is presently very common for compression of CD quality music. An MP3 decoder has a complex structure and is computationally demanding.

The purpose of this master's thesis is to present a tutorial on the standard. We have analysed several algorithms suitable for implementing an MP3 decoder, their advantages and disadvantages with respect to speed, memory demands and implementation complexity. We have also designed and implemented a portable reference MP3 decoder in C.

Documents

The thesis is available as a pdf file here. The source code appendix is in a separate pdf file here (and as a zip-file below).

Source Code

You will probably be interested in the following:

The thesis decoder source is designed to run on any standard Linux distribution.

License: My work is placed in the public domain. You may do whatever you wish with it, including using it for commercial applications. Please send any improvements back to me, and I'll include them in the source code. If you do so, that is under the assumption that your changes are also placed in the public domain.



Freevo

I started the Freevo project in late 2001, and wrote the original implementation from scratch. It quickly became popular, and many developers joined the project. One of them, Dischi, volunteered to continue managing it when I became more involved with other projects.


FPGA Forth CPU

The FPGA Forth CPU was a Master's design project at Chalmers University of Technology during 1998-1999. The goal was to implement a version of the Novix 4016 Forth CPU in an FPGA, and to write a simulator for it. There was a small (2K) boot-monitor called cmForth available.

The project was successful, both the FPGA implementation and the simulator works.

CPU Hardware Design Drawings

You can find the schematics here (PDF format).

The Novix architecture.

Simulator and FPGA implementation

The simulator code is written in C++ for Borland C++ Builder under Windows. The FPGA implementation was done with Xilinx Foundation 1.5 using schematic entry (not VHDL). It only uses low-level primitives and should be easy to port to other FPGA architectures.

Project Members

  • Krister Lagerström: Project leader, FPGA design
  • Magnus Lidman: Simulator programming
  • Carl Lom: Simulator programming
  • Bertil Jonell: FPGA design